JNTUH 2-1 ECE STLD Important Questions Unitwise
i. (6753)8 to base 10
ii. (00111101.0101)2 to base 8 and base 4
iii. (95.75)10 to base 2.(b) Represent +65 and -65 in sign-magnitude, sign-
1’s complement and sign–2’s Complement representation.
2.Given a = 10101001 and b = 1101
find:i. a + b ii. a –b iii. a . b iv. a / b.
3.What is the Gray code? What are the rules to construct Gray code? Developthe 4 bit Gray code for the decimal 0 to 15.
4.What are the rules for XS3 addition? Add the two decimal numbers 123 and 658 XS3 code.
i. Commutative ii. Associative iii. Distributive.
2.Simplify the following Boolean functions to minimum number of literals:
3. State Duality theorem. List Boolean laws and their Duals.
4. Prove that OR-AND network is equivalent to NOR-NOR network and AND-OR network isequivalent to NAND-NAND network
5.For the given Boolean function F=xy’z+x’y’z+w’xy+wx’y+wxy
i. Draw the logic diagram ii. Simplify the function to minimal literals using Boolean algebra.
1.Simplify the following Boolean expressions using K-map and implement them using NOR gates:
F (A, B, C, D) = AB’C’ + AC + A’CD’
2.List the Boolean function simplification rules using Tabulation method.
3.Simplify the Boolean function using K-map and implement using NAND gates
4.Reduce the given function using tabular minimization method
5.Simplify the Boolean expression using K-map F=A1+AB+ABD1+AB1D1+C
1.Implement the following Boolean functions using decoder and OR gates:
F1(A,B,C,D) = ∑(2,4,7,9), F2(A,B,C,D) = ∑(10,13,14,15)
2.What is Hazard in switching circuits? Explain the design of Hazard freeSwitching circuit with an example.
3.What is Encoder? Design Octal to Binary Encoder.
4.Design a combinational circuit that converts a decimal digit from 8, 4,-2,-1 code to 8,4,2,1 BCDcode.
5.Design a combinational circuit that accepts a 3 bit number and generates an output binarynumber equal to the square of the input number.
1.Implement the following boolean functions using PLA.
f1(w,x,y,z) = P(0,1,3,5,9,13) , f2 (w,x,y,z) = P(0,2,4,5,7,9,11,15).
2.The following memory units are specified by the no of words times the number of bits per word.How many address lines and input-output data lines are needed in each case?
i. 4K × 16 ii. 2G × 8 iii. 16M × 32 iv. 256K × 64. Give the number of bytes stored in thememories listed above
3.(a) Draw the basic macro cell logic diagram and explain.(b) Explain the general CPLD configuration with suitable block diagram.
4.For a given 3-input, 4-output truth table of a combinations ckt, tabulate the PAL programmingtable for the ckt.Inputs Outputx y z A B C D0 0 0 0 1 0 00 0 1 1 1 1 10 1 0 1 0 1 10 1 1 0 1 0 110 0 1 0 1 010 1 0 0 0 111 0 1 1 1 011 1 0 1 1 1
5. Write a brief notes on
a) Architecture of PLD’s. b)Capabilities and limitations of threshold gates.
1.Design Mod-6 synchronous counter using JKFF’s.
2.Explain the following
a.)Race around condition in FF’s.b) JK master slave FF. c)Excitation table for FF’s.
3.Draw the logic diagram of a SR latch using NOR gates. Explain its operation using excitation table.
4.(a) Draw the logic diagram of a 4 bit binary ripple counter using positive edge triggering.(b) Draw the block diagram of a 4 – bit serial adder and explain its operation.
5.a) Show that the characteristic equation for the complement out put of a JK flipflop is
Q ′(t + 1) = J ‘Q ′+ kQ.
b)Discuss about mod-
6 synchronous counter using JK FF’S.
1.Find the state table for the following state diagram
2.Draw the diagram of mealy-type FSM for serial adder.
3.(a) Draw the ckt for the moore type FSM.
x1(P,Q,R) =Σ(0,1,2,7), x2(P,Q,R) = Σ(1,4,5,6).
(b) Explain merger chart methods of minimal cover table.
4.Design a sequence detector which detects 110010 Implement the sequence detector by using D- type flipflops.
5. A clocked sequential circuit is provided with a single input x and single output Z.Whenever theinput produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce anoutputZ = 1 and overlapping is also allowed.(a) Obtain State – Diagram. (b) Also obtain state – Table. (c) Find equivalence classes usingpartition method & design the circuit using D- flip-flops.
1.For the given state diagram, as shown in figure obtain its ASM chart and Design the above circuitusing one flip flop per each state.
2.For the given control state diagram, draw the equivalent ASM chart and Design the controlcircuit using multiplexers
3.For the ASM chart given below, draw the state diagram and Design the control unit using D-flipflops and a decoder.
4.state diagram of a control unit iS
5.Draw the ASM chart for the following state transistion, start from the initialstate T1, then if xy=00 go to T2, if xy=01 go to T3, if xy=10 go to T1, otherwise go to T3.
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